Symbolic of the flexibility, extensibility and modularity of the RISC-V ISA, the RISC-V Electronic Badge designed by Antmicro in collaboration with the RISC-V Foundation and SiFive is completely open source, including the SiFive FE310 RISC-V SoC that drives it.
The RISC-V badge features an e-Ink screen to display the badgeholder’s name or whatever they will want to tell the RISC-V community.
The badge consists of a carrier card with a reusable, socket based small RISC-V SoC module that can be removed and used for prototyping other interesting RISC-V projects. The application runs Zephyr, an open source, Apache-licensed general purpose RTOS that covers multiple CPU architectures, including RISC-V.
In keeping with the open philosophy underpinning the RISC-V initiative, an open, free ISA enabling a new era of processor innovation through open standard collaboration, the RISC-V electronic badge is an open source and modular design symbolic of the flexibility, extensibility and modularity of the RISC-V ISA.