The RISC-V Badge: Open source to the core.

Symbolic of the flexibility, extensibility and modularity of the RISC-V ISA, the RISC-V Electronic Badge designed by Antmicro in collaboration with the RISC-V Foundation and SiFive is completely open source, including the SiFive FE310 RISC-V SoC that drives it.

Battery-powered and programmable over NFC from a smartphone.

The RISC-V badge features an e-Ink screen to display the badgeholder’s name or whatever they will want to tell the RISC-V community.

How is it built?

The badge consists of a carrier card with a reusable, socket based small RISC-V SoC module that can be removed and used for prototyping other interesting RISC-V projects. The application runs Zephyr, an open source, Apache-licensed general purpose RTOS that covers multiple CPU architectures, including RISC-V.




Get the files.

Open source to the core.

In keeping with the open philosophy underpinning the RISC-V initiative, an open, free ISA enabling a new era of processor innovation through open standard collaboration, the RISC-V electronic badge is an open source and modular design symbolic of the flexibility, extensibility and modularity of the RISC-V ISA.


HW source files (Altium Designer):

RISC-V Electronic Badge HW

RISC-V Electronic Badge HW

SW source files (C):

Zephyr RTOS application

Zephyr RTOS application

SoC source files (Chisel):

SiFive's Freedom platforms

SiFive's Freedom platforms